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10 Gbit/s Receiver, CDR and DeMUX GD16584/GD16588 (FEC)
Preliminary
General Description
GD16584 and GD16588 are Receiver chips for use in STM-64/192 and Optical Transport Networking (OTN) systems. The component is available in two versions: u GD16584 for 9.5328 Gbit/s. u GD16588 for 10.66 Gbit/s for OTN or Forward Error Correction (FEC). Except the different operating bit rates the two versions are functional identical. The receiver is a Clock and Data Recovery IC with: u a low noise VCO u a Bang-Bang Phase Detector u a 1:16 De-multiplexer u a Lock Detect u a Phase and Frequency Detector. Clock and data are regenerated by using a Phase Locked Loop (PLL) with an external passive loop filter. The VCO frequency is controlled by one of the two Phase Detectors in order to ensure capture and lock to the line data rate. The Lock Detector circuit monitors the VCO frequency and determines when the VCO is within the lock range. When the frequency deviates more than
VCO
VCTL Timing Control
Features
500 ppm from the reference clock, it automatically switches the phase and frequency detector into the PLL loop. In the auto lock mode the locking range is selectable between 500 or 2000 ppm. When the VCO frequency is within the lock range, the Bang-Bang Phase Detector takes over. It controls the phase of the VCO until the sampling point of data is in the middle of the bit period, where the eye opening is largest. A 40 mV Decision Threshold Control (DTC) is provided at the 10 Gbit/s input. The 10 Gbit/s input data is sampled and de-multiplexed by the 1:16 DeMUX. The parallel output interface is synchronised with the 622 MHz output clock. The clock and data outputs are LVDS compatible. The device operates from a dual -5.2 V and +3.3 V power supply. The power dissipation is 3.3 W, typical. The device is manufactured in a Silicon Bipolar process and packaged in an 132 ball 13 x 13 mm Ceramic/Plastic Ball Grid Array (BGA).
CKOUT CKOUTN
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Complete Clock and Data Recovery IC with auto acquisition. 1:16 DeMUX with differential 622 Mbit/s data outputs 622 MHz Clock output. LVDS compatible clock and data outputs. OIF99.102.5 compliant timing. 155 or 622 MHz Reference Clock. Input Decision Threshold Control (DTC): 40 mV. Low noise VCO with 5 % tuning range. Dual supply operation: -5.2 V and +3.3 V. Power dissipation: 3.3 W (typ). Silicon Bipolar technology. Available in three package versions: - EB: 132 ball (16 mill) Ceramic BGA 13 x 13 mm - EF: 132 ball (20 mill) Ceramic BGA 13 x 13 mm - FB: 132 ball (20 mill) Plastic BGA 13 x 13 mm Available in two versions: - GD16584 for 10 Gbit/s - GD16588 for 10.66 Gbit/s
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DO0 DON0 DI DIN
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DTC DTCN
Decision Threshold Control
Bang Bang Phase Detector
1:16 Demultiplexer
Parallel Output Data DO15 DON15
U
REFCK REFCKN
Phase Frequency Detector
1/4
D
PCTL
Applications
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(PHIGH) (PLOW)
Lock Detect
LOCK
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Telecommunication systems: - SDH STM-64 - SONET OC-192. - Optical Transport Networking (OTN) - FEC applications Fibre optic test equipment. Submarine systems.
Data Sheet Rev.: 12
RESET
TCK
SEL3
SEL1
SEL2
VCC
VDD
VDDA
VDDO
VEE
VEEA
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Functional Details
The application of GD16584 is as receiver in SDH STM-64 and SONET OC-192 optical communication systems. It integrates: u a Voltage Controlled Oscillator (VCO) u a Bang Bang Phase Detector u a Lock Detect Circuit u a 1:16 DeMUX u a Phase and Frequency Detector (PFD).
Loop Filter
A passive loop filter is used for the CMU consisting of a resistor and a capacitor driven from the PCTL pin. The PCTL pin outputs the phase information from the Bang-Bang Phase Detector. The phase information is very high frequency pulses (200 ps pulse width) either charging or discharging the external capacitor. The values of the external components determines the characterisctics of the PLL, e.g. bandwidth and transfer functions. For recommended loop filter values, please refer to Figure 1. The PCB lay-out of the external loop filter and the connecting lines between PCTL and VCTL are critical for jitter performance of the device. The external components and the artwork should be placed very close to the pins of the device. If the PHIGH and PLOW outputs are not used they must be shorted VDD (0 V), please refer to Figure 1.
and DIN) whereby the DC bias voltage at the input is adjustable by 40 mV. Optimizing the input decision threshold improves the system input sensitivity by 1-2 dB typical. The input impedance into DTC and DTCN is 1.5 kW and when not used they should be de-coupled to 0 V by 100 nF. The select inputs (SEL1-3, RESET and TCK) are low speed inputs that can be connected directly to the supply rails (0 / -5.2 V). The 10 Gbit/s inputs (DI and DIN) are not ESD protected and extra precautions are needed when handling these inputs. (Internal 50 W resistors provide some ESD hardness making the input low impendance.)
VCO
The VCO is an LC-type differential oscillator, voltage controlled by pin VCTL and with a tuning range of approximately 5 %. For GD16584, with the VCTL voltage at approximately -3.5 V, the VCO frequency is fixed at 9.953 GHz and by changing the voltage from 0 to -5.2 V the frequency is controlled from 8.9 GHz to 10.2 GHz. The modulation bandwidth of VCTL is 90 MHz.
Bit Order
The serial data stream is demultiplexed with the first received bit on DO0, the second on DO1 and with last received bit in a 16 bit frame on DO15. The naming is opposite to the OIF99.102.5 recommendation. For OIF interfaces the data pins should be connected as shown in the following table. Note: The clock output is inverted in order to refer the data crossing to the rising edge of CKOUTN OIF: RXDATA15_P/N (MSB) RXDATA14_P/N RXDATA13_P/N RXDATA12_P/N RXDATA11_P/N RXDATA10_P/N RXDATA9_P/N RXDATA8_P/N RXDATA7_P/N RXDATA6_P/N RXDATA5_P/N RXDATA4_P/N RXDATA3_P/N RXDATA2_P/N RXDATA1_P/N
PFD
The PFD ensures predictable locking conditions for the device. It is used during acquisition and pulls the VCO into the locking range where the Bang-Bang Phase Detector acquires lock to the incoming bit-stream. The PFD is made with digital set/reset cells giving it a true phase and frequency characteristic. The reference clock input (REFCK/REFCKN) to the PFD is differential and selectable between 155 MHz or 622 MHz by SEL3. The reference clock is a CML input with 50 W internal termination resistors to 0 V. The reference clock is typically an X-tal oscillator type as shown in Figure 1. The reference clock input should be used differential for best performance. If the reference clock is DC coupled the input voltage swing is 0 V (high) and -0.4 V (low).
Lock Detect Circuit
The lock detect circuit continuously monitors the difference between the reference clock and the VCO clock. If they differ by more than 500 ppm (or 2000 ppm), it switches the PFD into the PLL, to pull it back into the locking range. The status of the lock circuit is given by output pin (LOCK). Manual or automatic lock is selected by SEL1. In auto lock mode, the lock range 500 or 2000 ppm is selected by SEL2. The LOCK output is an open collector output, and should be terminated with an external resistor. The maximum termination voltage is +3.5 V.
Output Pin: DO0/DON0 DO1/DON1 DO2/DON2 DO3/DON3 DO4/DON4 DO5/DON5 DO6/DON6 DO7/DON7 DO8/DON8 DO9/DON9 DO10/DON10 DO11/DON11 DO12/DON12 DO13/DON13 DO14/DON14
The Inputs
The input amplifier pin (DI/DIN) is designed as a gain buffer stage with high sensitivity and internal 50 W resistors terminated to 0 V. After retiming, the data is de-multiplexed down to 16 bit/s by demultiplexer. It is recommended to use the 10 Gbit/s inputs differentially for best input sensitivity. The input voltage decision threshold is adjustable by pin DTC and DTCN when connected to a potentiometer. Adjusting the resistor value of the meter controls the current into DTC and DTCN. This DC current is mirrored to the input pin (DI
Bang-Bang Phase Detector
The Bang-Bang phase detector is designed as a true digital type producing a binary output. It samples the incoming data prior to, in the vicinity of and after any potential bit transition. When a transition has occurred, these three samples tell whether the VCO clock leads or lags the data. The binary output is filtered through the (low pass) loop filter, performing an integration of all potential bit transitions. Hence the PLL is controlled by the bit transition point.
Data Sheet Rev.: 12
GD16584/GD16588
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Output Pin: www..com DO15/DON15 CKOUT CKOUTN
OIF: RXDATA0_P/N (LSB) RXCLK_N RXCLK_P
Thermal Condition
The device dissipates 3.3 W from a dual voltage supply (-5.2 V and +3.3 V). The power consumption from the -5.2 V supply is approximately 2.9 W and 0.4 W from the +3.3 V supply. The die is mounted on a metal pad directly connected to the center balls (E4-9, F4-9, G4-9, and H4-9). It is important to have a good thermal connection from the center balls of the package via the PCB to the ambient environment to ensure the best thermal conditions. Note: To obtain TCASE < 70C, the PGBA requires (compared to the CBGA) additional cooling on the case. For details, please refer to Application Note " PBGA Thermal data....".
The Outputs
The data and clock outputs are LVDS compatible outputs with internal bias resistors (500 W) to VCC (+3.3 V) Refer to item "LVDS Compatible Interface" on page 6.
Timing to System ASIC
The timing between GD16584 and the system ASIC at 622 Mbit/s is controlled by the 622 MHz output clock synchronized with the output data. The clock is used as the input clock to the ASIC, clocking the input data into 16 parallel registers. The timing relation between the clock and data is given by the AC Characteristics. For a OIF99.102.5 complaint timing the output clock should be inverted by using: u CKOUTN as the positive output clock (RXCLK_P), and u CKOUT as the negative output clock (RXCLK_N)
10.66 Gbit/s Application
A version of the transmitter with a bit rate of 10.66 Gbit/s for forward error correction application is available. The part number is GD16588. The functionality and the pin-out are identically to GD16584. The center frequency of the VCO (10.66 GHz) is the only difference to GD16584.
External Circuit
The external circuits needed to make the device work as a complete clock and data recovery with automatic acquisition are: u A passive loop filter u An X-tal oscillator or reference clock (155 MHz or 622 MHz) u De-coupling capacitors
Package
The device is packaged in an 132 ball Ceramic/Plastic BGA (13 x 13 mm). For the package outline, please refer to the Figures on page 13 and 14. In ceramic package the following pin pairs are individually shorted inside the package and mainly used as power pins: C3/D3, C4/D4, C5/D5, C8/D8, C9/D9, C10/D10, J3/K3, J4/K4, J5/K5, J8/K8, J9/K9, and J10/K10.
Data Sheet Rev.: 12
GD16584/GD16588
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Applications
1
+3.3V 0V
VDD/VDDA/VDDO TCK RESET
VCC
0V -5.2V
1 0
0V -5.2V 0V -5.2V 50W MSL VDD 50W MSL
Framer SEL1 SEL2 SEL3 CKOUT CKOUTN DO0..DO15 DON0..DON15
16 16
1 0
10Gbit/s CML Driver
DI DIN
GD16584/GD16588
0V
VDD 220
DTC
10k 0V
LOCK
330W VREF VDD
+ -5.2V
DTCN REFCK
14
8 7
330
43
100nF
XO-PECL 155/622 MHz KVG
-5.2V
500W
-5.2V
PLOW REFCKN PHIGH VCTL PCTL
150W 33nF
100nF
500W
VDDA
-5.2V
-5.2V
VEE/VEEA
-5.2V
Figure 1.
Application Information.
VDD VEE VDDO VEEA
Pin A1 C
Pin A4 C C C C
VDD pins refer to Pin List
C C C C C
Pin K4 Pin M12 C C 10mF
Pin C2 C
Pin B2 C
VDDA
10mF
VCC VDD
Pin D11 Pin K12 C C 10mF
C is 1000nF parallel with 100pF.
VEE pins refer to the Pin List; VEEA pins C3 and D3
Figure 2.
De-coupling of the Power Supply. GD16584/GD16588 Page 4 of 15
Data Sheet Rev.: 12
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Applications Continued
10 Gbit/s Input Interface
Postamplifier GD16584/GD16588
0V 0V 50W 0/-0.4V 0/-0.4V 50W MSL DI DIN 50W 50W
>16mA
-5.2V
Figure 3.
10 Gbit/s Input (DI/DIN), DC Coupled
GD16584/GD16588
0V -5.2V 50W 50W
Postamplifier
50W MSL
220W DI 100nF 220W -5.2V -5.2V DIN
Figure 4.
10 Gbit/s Input (DI/DIN), AC Coupled
Data Sheet Rev.: 12
GD16584/GD16588
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LVDS Compatible Interface
GD16584 or GD16585
500W +3.3V +3.3V
VCC
500W
LVDS Input
50W MSL 100W
0V 8mA
-5.2V
Figure 5.
LVDS Compatible Output.
Reference Clock Input
GD16584
0V 50W
0V
-5.2V 500W
REFCK REFCKN
100nF
500W -5.2V -5.2V
Figure 6.
Reference Clock Input (REFCK/REFCKN), Differential AC Coupled.
Data Sheet Rev.: 12
GD16584/GD16588
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Pin List
DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9,
Mnemonic: DON0 DON1 DON2 DON3 DON4 DON5 DON6 DON7 DON8 DON9
Pin No.: A8, B8 A9, B9 A10, B10 A11, A12 C11, C12 D12, E12 G11, H12 J12, J11 M11, L10 M10, L9 M9, L8 L6, K6 M5, L5 L4, M3 M2, M1 K3, L2 A5, A6 C5, B5
Pin Type: LVDS Out
Description: Data output, differential 622 Mbit/s. Demultiplexed to output with DO0, DO1...DO15 as first received bits. Note: The bit naming convention is opposite to OIF99.102.5: DO0 is MSB. Please refer to item "Bit Order" on page 2.
DO10, DON10 DO11, DON11 DO12, DON12 DO13, DON13 DO14, DON14 DO15, DON15 REFCK, REFCKN SEL1, SEL2
CML In ECL In
Reference clock input, differential 155 MHz or 622 MHz. Clock and Data recovery setup. SEL1 SEL2 0 0 Auto Lock, 500 ppm. 0 1 Auto Lock, 2000 ppm. 1 0 Manual Phase Freq. Detector (PFD). 1 1 Manual Bang-Bang Phase Detector. When left open, the inputs are pulled to VDD.
SEL3
K11
ECL In
SEL3 0 155 MHz Reference Clock. 1 622 MHz Reference Clock. When left open, the input is pulled to VDD. Data input, differential 10 Gbit/s. No ESD input protection. Clock output, differential 622 MHz. Note: The clock polarity is opposite to OIF99.102.5. Please refer to item "Bit Order" on page 2 and Figure 1. Lock detect output. When low, the divided VCO frequency deviates more than 500/2000 ppm from REFCK/REFCKN, should always be terminated with a resistor to VDD. Charge pump output. Connected to an external passive loop filter. VCO voltage control input. Decision threshold control. Not used. Always terminate to VDD. Connect to VDD. Used for test purpose. When left open, the input is pulled to VDD. Connect to VEE. Not needed on power up, used for test purpose. Digital Ground 0 V.
DI, DIN CKOUT, CKOUTN
H1, E1 L12, L11
CML In LVDS Out
LOCK
C6
Open Collector
PCTL VCTL DTC, DTCN (PHIGH, PLOW) TCK RESET VDD
B3 B1 M6, K5 A3, B4 C1 L1 A1, A4, B6, C10, D1-2, D6, D10, E4-9, F1-2, F4-9, F11, G1-2, G4-9, H4-9, J1-2, J4, J7, K4, M12 B2 C2 D11, K12
Analogue Out Analogue In Analogue In Open Collector ECL In ECL In PWR
VDDA VDDO VCC
PWR PWR PWR
PLL Ground 0 V. VCO Ground 0 V. For test purpose, connect to VEE. +3.3 V Digital supply voltage.
Data Sheet Rev.: 12
GD16584/GD16588
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Mnemonic: www..com VEE
Pin No.: C4, C8, D4, D7-8, J8-9, K1, K8-9 C3, D3 A2, A7, B7, B11-12, C7, C9, D9, F12, G12, J6, J10, K2, K7, K10, L3, L7, M4, M7-8, D5, J3, J5
Pin Type: PWR PWR
Description: -5.2 V Digital supply voltage. -5.2 V PLL supply voltage. Not Connected. Reserved for future use.
VEEA NC
NC
DO NOT CONNECT
Package Pinout
1 A B C D E F G H J K L M
VE E ET 14 NC N DO DO 15 DI NC DO 15 DO 13 NC DT CN 12 NC N DO DO 11 NC NC NC VE VE E VE VE DO E NC NC DO N8 9 DO N7 L3 N DO 6 DIN VC TL K
2
NC VD VD DA
3
IG (PH PC VE H)
4
5
F RE CK
6
F RE CK N
7
NC NC
8
DO DO 0
9
DO DO 1
10
DO DO 2
11
DO 3
12
DO N3
A B C D E F G H J K L M
TL
O (PL VE
W)
SE
L2 L1 LO CK
N0 E E
N1
N2
NC DO VC 4
NC DO N4 5
TC
DO
EA EA
E E
SE
NC VE E
VE
NC NC
VE
VE
NC
VE
C
DO DO
N5
NC NC DO N6 7
DO VC
E 10
E
SE O CK
C UT
S RE
NC N DO 13
N DO DO
11 C
N DO
N9 10
UT 8
O CK
N DO
14
NC
12
DT
NC
DO
DO
DO
1
2
3
4
5
XX X
6
7
8
9
10
11
12
(empty) = VDD
X XX
= Internally shorted in the package
Figure 7.
Packages EB and EF Pinout. Top View - Seen Through the Package
Data Sheet Rev.: 12
GD16584/GD16588
Page 8 of 15
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1
2
NC
3
IG (PH PC VE H)
4
5
F RE CK
6
F RE CK N
7
NC NC
8
DO DO 0
9
DO DO 1
10
DO DO 2
11
DO 3
12
DO N3
A B C D E F G H J K L M
VE E ET 4 DI DIN VC TL K
A B C D E F G H J K L M
VD VD
DA
TL
O (PL VE
W)
SE
L2 L1 LO CK
N0 E E
N1
N2
NC DO VC 4
NC DO N4 5
TC
DO
EA EA
E E
SE
NC VE E
VE
NC NC
VE
VE
NC
VE
C
DO DO
N5
NC DO 6 NC DO NC NC N DO DO 15 DO 15 DO 3 13 NC DT CN 12 NC DO 1 N1 11 C NC NC NC VE VE E VE VE E NC NC N DO DO 8 C DO N7 L3 N6 7
DO VC
E 10
E 9
SE
C
S RE DO
NC DO N1
N DO DO
DO
N DO
N DO DO
U KO DO
T TN OU CK
N1
14
NC
12
DT
NC
10
9
8
1
2
3
4
5
XX XX X
6
7
8
9
10
11
12
(empty) = VDD
X
= Internally shorted in the package
Figure 8.
Package FB Pinout. Top View - Seen Through the Package
Data Sheet Rev.: 12
GD16584/GD16588
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Maximum Ratings
These are the limits beyond which the component may be damaged. All voltages in table are referred to VDD. All currents are defined positive out of the pin. VDD is 0 V or GND. Symbol: VEE VCC VO LVDS IO LVDS VI CML, ECL II CML VO OC IO OC V ESD TJ TS Note 1: Note 2: Note 3: Note 4: Characteristic: Negative Supply Positive Supply LVDS Output Voltage LVDS Output Current CML and ECL Input Voltage CML Input Current Open Collector Output Voltage Open Collector Output Current Static Discharge Voltage Junction Temperature Storage Temperature Note 1 HBM, Note 3 CDM, Note 4 Note 2 -55 -65 Note 1 Note 1 0 -24 VEE +2 -24 VEE -0.5 -12 Conditions: MIN.: -6 TYP.: MAX.: 0 +4 VCC +0.5 24 0.5 24 0 0 500 50 +125 +125 UNIT: V V V mA V mA V mA V V C C
Nominal supply voltages. The maximum junction temperature equals a maximum case temperature of 95 C (top side) with the device mounted on the GD90584/585 Evaluation Board. Human Body Model: MIL 883D 3015.7 standard. Charge Device Model.: JESD2-C101 standard.
Data Sheet Rev.: 12
GD16584/GD16588
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DC Characteristics
TCASE* = 0 C to 70 C. VEE = -5.2 V, VCC = +3.3 V. VDD is 0 V or GND. All voltages in table are referred to VDD. All currents are defined positive out of pin. Symbol: VEE IEE VCC ICC VOH LVDS VOL LVDS VOD LVDS VIH CML VIL CML IIH CML IIL CML RIN CML IOH OC IOL OC VIH ECL VIL ECL IIH ECL IIL ECL VADS Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: *: Characteristic: Negative Supply Voltage Negative Supply Current Positive Supply Voltage Positive Supply Current LVDS Output Voltage High LVDS Output Voltage Low LVDS Output Differential Voltage CML Input Voltage High CML Input Voltage Low CML Input Current High CML Input Current Low CML Input Resistor Termination Open Collector Output Current High Open Collector Output Current Low ECL Input Voltage High ECL Input Voltage Low ECL Input Current High ECL Input Current Low Offset Adjustment by DTC/DTCN, Differential VIH CML, 50 W input VIL CML, 50 W input DC Note 1, 3 Note 1, 3 Note 2, 5 Note 2, 5 V = -1.1 V V = -1.5 V Note 4, 6 90 40 -0.1 -10 -1.1 VEE Note 7, VCC = 3.3 V Note 7, VCC = 3.3 V Note 7, VCC = 3.3 V 0.9 250 -0.1 -1 Conditions: MIN.: -5.46 455 3.135 -180 TYP.: -5.2 550 3.3 -140 1.4 1.1 400 0 -0.4 0 8 50 0 -8 60 +0.1 -7 0 -1.5 30 30 600 +0.1 -0.25 1.5 MAX.: -4.94 660 3.465 UNIT: V mA V mA V V mV V V mA mA W mA mA V V mA mA mV
Output externally terminated by 50 W to 0 V. All ECL inputs can be connected directly to VDD/VEE. All open collector outputs should always be terminated with a resistor. With DTC and DTCN connected to a 10k potentiometer with the mid pin grounded (0 V). -5.0 V. With open data inputs. With 100 W termination resistor. TCASE measured at the center of the top.
Data Sheet Rev.: 12
GD16584/GD16588
Page 11 of 15
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AC Characteristics
TCASE* = 0 C to 70 C. VEE = -5.2 V, VCC = +3.3 V.
CKOUT CKOUTN DO0-15
tD
Figure 9. Symbol: JTol tD V DI/DIN G DI/DIN DCYCLE CKOUT/N F REFCK/N DC DCYCLE REFCK/N Note 1: Note 2: Note 3: Note 4: *: OIF99.102.5 complaint timing relation between the negative output clock (CKOUTN) and output data (DO0-15). Characteristic: Jitter tolerance Conditions: f < 400 kHz 4 MHz < f Note 4 MIN.: 1.5 0.15 0 Note 2 Note 3 45 Note 1 -100 40 155/622 100 60 120 100 -10 55 200 TYP.: MAX.: UNIT: UI
Delay between DO0-15 and CKOUT/CKOUTN Data input sensitivity, differential DI/DIN input reflection coefficient CKOUT/CKOUTN duty cycle REFCK/REFCKN frequency REFCK frequency deviation from nominal line frequency REFCK duty cycle
ps mVPP dB % MHz ppm %
Selectable by SEL3. BER = 10-9 From DC to 6 GHz. Depends on lead length, board, soldering etc. of the component. Measured with the recommended loop filter, see Figure 1. TCASE measured at the center of the top.
Data Sheet Rev.: 12
GD16584/GD16588
Page 12 of 15
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Package Outline
EF - Package
Figure 10. Package 132 ball ceramic BGA (EB and EF package). All dimensions are in mm.
Data Sheet Rev.: 12
GD16584/GD16588
Page 13 of 15
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Figure 11. Package 132 ball plastic BGA (FB package). All dimensions are in mm.
Data Sheet Rev.: 12
GD16584/GD16588
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Device Marking
GD16584- -
GD16588- -
Figure 12. Device marking. Top view. The black square marks location of ball A1.
Ordering Information
To order, please specify as shown below: Product Name: Version: 10 Gbit/s 10 Gbit/s 10 Gbit/s 10.66 Gbit/s 10.66 Gbit/s 10.66 Gbit/s Package Type: 132 ball (16 mill) Ceramic BGA 132 ball (20 mill) Ceramic BGA 132 ball (20 mill) Plastic BGA 132 ball (16 mill) Ceramic BGA 132 ball (20 mill) Ceramic BGA 132 ball (20 mill) Plastic BGA Intel Order Number: Case Temperature Range: 0..70 C 0..70 C 0..70 C 0..70 C 0..70 C 0..70 C
GD16584-EB GD16584-EF GD16584-FB GD16588-EB GD16588-EF GD16588-FB
HCGD16584EB
MM# 835478 MM# 837347 MM# 836957 MM# 835480 MM# 837349 MM# 836962
HCGD16584EF RCGD16584FB HCGD16588EB HCGD16588EF RCGD16588FB
GD16584/GD16588, Data Sheet Rev.: 12 - Date: 2 November 2001
an Intel company
Mileparken 22, DK-2740 Skovlunde Denmark Phone : +45 7010 1062 Fax : +45 7010 1063 E-mail : sales@giga.dk Web site : http://www.intel.com/ixa
Please check our Internet web site for latest version of this data sheet.
The information herein is assumed to be reliable. GIGA assumes no responsibility for the use of this information, and all such information shall be at the users own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. GIGA does not authorise or warrant any GIGA Product for use in life support devices and/or systems.
Distributor:
Copyright (c) 2001 GIGA ApS An Intel company All rights reserved

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